The ability to generate repeatable, highly precise time delay increments is critical in many digital signal processing systems. Automated testing systems, for example, of the type used to test Very Large Scale Integrated (VLSI) logic circuits and memory arrays require the ability to generate selectable time delays accurate in the picosecond (ps) range.
Because such testing systems are used to test chips having input/output (I/O) pin counts which may approach or even exceed 200-500 in number, highly accurate signal delays of the above-described type must be generated in proportionately large quantities: i.e. for a high percentage of the I/O pins. Thus, circuits for generating such delays must not only be capable of providing the required accuracy, but must also be economical in size and cost so as to be practical for use in large quantities.
U.S. Pat. No. 4,016,511 to Ramsey et al. shows a programmable, variable length digital delay circuit wherein clocked, shift register delay devices of variable lengths are interconnected by digitally controllable switches. Control of the switches effects control of the delay. However, the Ramsey et al. circuit suffers from the disadvantage of having time delay increments limited to the clock speed used to clock the registers. Further, the Ramsey et al. circuit requires the implementation of a relatively complex, expensive switching arrangement.
U.S. Pat. No. 3,781,822 to Ahamed shows a data rate-changing and reordering circuit wherein a plurality of series-connected stages are provided, each stage including a pair of parallel delay paths, each delay path providing a different delay time. In Ahamed, the outputs of each pair of delay paths are connected such that data sent through the different paths is recombined in a desired order. The actual delay times in the various paths are selected not to provide adjustable fine delays, but to effect a desired rate-change or reordering of the processed data.
U.S. Pat. No. 3,526,840 to Wheaton, Jr. shows a steering and timing circuit comprising multiple, series connected stages, each stage including a pair of parallel paths, each path providing a different delay time. In Wheaton, Jr., the first path is a minimal delay path through a gate, while the second path is a longer delay path through a monostable multivibrator. Such an arrangement could not provide the fine delay times provided by the subject invention.
U.S. Pat. No. 4,737,670 to Chan shows a circuit for generating a constant delay between an input and an output, regardless of changes in gate delays due to variable factors such as temperature and power supply voltage levels. The circuit includes a ring oscillator circuit constructed on the same semiconductor chip as a variable delay circuit. The frequency of the ring oscillator circuit is measured periodically, and used to select the appropriate delay. Thus, if the frequency of the ring oscillator circuit changes, the appropriate variable delay is selected to provide the desired constant delay. The subject system is designed to provide a constant delay, and not the programmable, selectable delay of the present invention.
U.S. Pat. No. 4,504,749 to Yoshida shows a delay pulse generating circuit which uses a variable delay in a circuit for generating a desired delay. The variable delay is connected in a feedback loop so as to oscillate during a calibration period. The oscillation frequency is measured, the delay through the circuit is calculated and compared with a desired delay, and a circuit is provided for adjusting the variable delay to achieve the desired delay. A binary search routine is provided for adjusting the variable delay to achieve the desired delay. As with the patent to Chan, described above, the subject patent is directed to a circuit which is calibrated to provide a single, accurate delay.